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ADG728/adg729 a rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. cmos, low-voltage, 2-wire serially-controlled, matrix switches one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 functional block diagrams s1 s8 sda d scl ADG728 s1a da s4a s1b s4b db adg729 reset input shift register input shift register a0 a1 sda scl a0 a1 i 2 c is a trademark of philips corporation. features 2-wire serial interface 2.7 v to 5.5 v single supply 2.5 on resistance 0.75 on-resistance flatness 100 pa leakage currents single 8-to-1 matrix switch ADG728 dual 4-to-1 matrix switch adg729 power-on reset small 16-lead tssop package applications data acquisition systems communication systems relay replacement audio and video switching automatic test equipment general description the ADG728 and adg729 are cmos analog matrix switches with a serially controlled 2-wire interface. the ADG728 is an 8-channel matrix switch, while the adg729 is a dual 4-channel matrix switch. on resistance is closely matched between switches and very flat over the full signal range. these parts can operate equally well as either multiplexers, demultiplexers or switch arrays and the input signal range extends to the supplies. the ADG728 and adg729 utilize a 2-wire serial interface that is compatible with the i 2 c interface standard. both have two external address pins (a0 and a1). this allows the 2 lsbs of the 7-bit slave address to be set by the user. four of each of the devices can be connected to the one bus. the ADG728 also has a reset pin that should be tied high if not in use. each channel is controlled by one bit of an 8-bit word. this means that these devices may be used in a number of different con?urations; all, any, or none of the channels may be on at any one time. on power-up of the device, all switches will be in the off con- dition and the internal shift register will contain all zeros. all channels exhibit break-before-make switching action pre- venting momentary shorting when switching channels. the ADG728 and adg729 are available in 16-lead tssop packages. product highlights 1. 2-wire serial interface. 2. single supply operation. the ADG728 and adg729 are fully speci?d and guaranteed with 3 v and 5 v supply rails. 3. low on resistance 2.5 ? typical. 4. any con?uration of switches may be on at any one time. 5. guaranteed break-before-make switching action. 6. small 16-lead tssop package.
C2C rev. a ADG728/adg729?pecifications 1 (v dd = 5 v 10%, gnd = 0 v, unless otherwise noted.) b version ?0 c parameter 25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on ) 2.5 ? typ v s = 0 v to v dd , i s = 10 ma; 4.5 5 ? max test circuit 1 on-resistance match between 0.4 ? typ v s = 0 v to v dd , i s = 10 ma channels ( ? r on ) 0.8 ? max on-resistance flatness (r flat(on) ) 0.75 ? typ v s = 0 v to v dd , i s = 10 ma 1.2 ? max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v, test circuit 2 0.1 0.3 na max drain off leakage i d (off) 0.01 na typ v d = 4.5 v/1 v, v d = 1 v/4.5 v, test circuit 3 0.1 1 na max channel on leakage i d , i s (on) 0.01 na typ v d = v s = 4.5 v/1 v, test circuit 4 0.1 1 na max logic inputs (a0, a1) 2 input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ 0.1 a max c in , input capacitance 6 pf typ logic inputs (scl, sda) 2 input high voltage, v inh 0.7 v dd v min v dd + 0.3 v max input low voltage, v inl ?.3 v min 0.3 v dd v max i in , input leakage current 0.005 a typ v in = 0 v to v dd 1.0 a max v hyst , input hysteresis 0.05 v dd v min c in , input capacitance 6 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on 95 ns typ r l = 300 ? , c l = 35 pf, test circuit 5; 140 ns max v s1 = 3 v t off 85 ns typ v s1 = 3 v, r l = 300 ? , c l = 35 pf; 130 ns max test circuit 5 break-before-make time delay, t d 8 ns typ r l = 300 ? , c l = 35 pf; 1ns minv s1 = v s2 = 3 v, test circuit 5 charge injection 3 pc typ v s = 2.5 v, r s = 0 ? , c l = 1 nf; test circuit 6 off isolation ?5 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz; ?5 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 channel-to-channel crosstalk ?5 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz; ?5 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 ? db bandwidth ADG728 65 mhz typ r l = 50 ? , c l = 5 pf, test circuit 8 adg729 100 mhz typ c s (off) 13 pf typ c d (off) ADG728 85 pf typ adg729 42 pf typ c d , c s (on) ADG728 96 pf typ adg729 48 pf typ power requirements v dd = 5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v 20 a max n otes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. speci?ations subject to change without notice.
C3C rev. a ADG728/adg729 (v dd = 3 v 10%, gnd = 0 v, unless otherwise noted.) specifications 1 b version ?0 c parameter 25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )6 ? typ v s = 0 v to v dd , i s = 10 ma; 11 12 ? max test circuit 1 on-resistance match between 0.4 ? typ v s = 0 v to v dd , i s = 10 ma channels ( ? r on ) 1.2 ? max on-resistance flatness (r flat(on) ) 3.5 ? typ v s = 0 v to v dd , i s = 10 ma leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v, test circuit 2 0.1 0.3 na max drain off leakage i d (off) 0.01 na typ v d = 3 v/1 v, v d = 1 v/3 v, test circuit 3 0.1 1 na max channel on leakage i d , i s (on) 0.01 na typ v d = v s = 3 v/1 v, test circuit 4 0.1 1 na max logic inputs (a0, a1) 2 input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current i inl or i inh 0.005 a typ 0.1 a max c in , input capacitance 3 pf typ logic inputs (scl, sda) 2 input high voltage, v inh 0.7 v dd v min v dd + 0.3 v max input low voltage, v inl ?.3 v min 0.3 v dd v max i in , input leakage current 0.005 a typ v in = 0 v to v dd 1.0 a max v hyst , input hysteresis 0.05 v dd v min c in , input capacitance 3 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on 130 ns typ r l = 300 ? , c l = 35 pf, test circuit 5; 200 ns max v s1 = 2 v t off 115 ns typ r l = 300 ? , c l = 35 pf; 180 ns max v s = 2 v, test circuit 5 break-before-make time delay, t d 8 ns typ r l = 300 ? , c l = 35 pf; 1ns minv s1 = v s8 = 2 v, test circuit 5 charge injection 3 pc typ v s = 1.5 v, r s = 0 ? , c l = 1 nf; test circuit 6 off isolation ?5 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz; ?5 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 8 crosstalk ?5 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz; ?5 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 7 ? db bandwidth ADG728 65 mhz typ r l = 50 ? , c l = 5 pf, test circuit 8 adg729 100 mhz typ c s (off) 13 pf typ c d (off) ADG728 85 pf typ adg729 42 pf typ c d , c s (on) ADG728 96 pf typ adg729 48 pf typ power requirements v dd = 3.3 v i dd 10 a typ digital inputs = 0 v or 3.3 v 20 a max notes 1 temperature ranges are as follows: b versions: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. speci?ations subject to change without notice.
C4C rev. a ADG728/adg729 timing characteristics 1 parameter limit at t min , t max unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 ms min scl cycle time t 2 0.6 ms min t high , scl high time t 3 1.3 ms min t low , scl low time t 4 0.6 ms min t hd, sta , start/repeated start condition hold time t 5 100 ns min t su, dat , data setup time t 6 2 0.9 ms max t hd, dat , data hold time 0ms min t 7 0.6 ms min t su, sta , setup time for repeated start t 8 0.6 ms min t su, sto , stop condition setup time t 9 1.3 ms min t buf , bus free time between a stop condition and a start condition t 10 300 ns max t r , rise time of both scl and sda when receiving 20 + 0.1c b 3 ns min t 11 250 ns max t f , fall time of sda when receiving 300 ns max t f , fall time of sda when transmitting 0.1c b 3 ns min c b 400 pf max capacitive load for each bus line t sp 4 50 ns max pulsewidth of spike suppressed notes 1 see figure 1. 2 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the unde?ed region of the falling edge of scl. 3 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd . 4 input ?tering on both the scl and sda inputs suppress noise spikes which are less than 50 ns. speci?ations subject to change without notice. t 3 t 2 t 1 t 4 t 8 t 6 t 5 t 9 t 7 t 4 t 11 t 10 sda scl start condition start condition repeated start condition stop condition figure 1. 2-wire serial interface timing diagram (v dd = 2.7 v to 5.5 v. all speci?ations ?0 c to +85 c, unless otherwise noted.)
ADG728/adg729 C5C rev. a ordering guide model temperature range package description package option ADG728bru ?0 c to +85 c thin shrink small outline package (tssop) ru-16 adg729bru ?0 c to +85 c thin shrink small outline package (tssop) ru-16 pin function descriptions ADG728 adg729 mnemonic function 1 1 scl serial clock line. this is used in conjunction with the sda line to clock data into the 8-bit input shift register. clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface. 2 reset active low control input that clears the input register and turns all switches to the off condition. 3 3 sda serial data line. this is used in conjunction with the scl line to clock data into the 8-bit input shift register during the write cycle and used to read back 1 byte of data during the read cycle. it is a bidirectional open-drain data line which should be pulled to the supply with an external pull-up resistor. 4, 5, 6, 7 4, 5, 6, 7 sxx source. may be an input or output. 8 8, 9 dx drain. may be an input or output. 9, 10, 11, 12 10, 11, 12, 13 sxx source. may be an input or output. 13 14 v dd power supply input. these parts can be operated from a supply of 2.7 v to 5.5 v. 14 15 gnd ground reference. 15 2 a1 address input. sets the second least signi?ant bit of the 7-bit slave address. 16 16 a0 address input. sets the least signi?ant bit of the 7-bit slave address. adg729 scl s2a s3a s4a s1a da 1 2 16 15 5 6 7 12 11 10 3 4 14 13 8 9 top view (not to scale) a1 gnd v dd sda adg729 a0 s2b s3b s4b s1b db ADG728 scl reset s2 s3 s4 s1 d 1 2 16 15 5 6 7 12 11 10 3 4 14 13 8 9 top view (not to scale) a1 s5 s6 s7 gnd v dd s8 sda ADG728 a0 pin configurations
C6C rev. a ADG728/adg729 absolute maximum ratings 1 (t a = 25 c unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v analog, digital inputs 2 . . . . . . . . . . ?.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, each s . . . . . . . . . . . . . . . . . . . . . 30 ma continuous current d, adg729 . . . . . . . . . . . . . . . . . 80 ma continuous current d, ADG728 . . . . . . . . . . . . . . . . 120 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADG728/adg729 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. tssop package ja thermal impedance . . . . . . . . . . . . . . . . . . . 150.4 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . 27.6 c/w lead temperature, soldering (10 seconds) . . . . . . . . . . 300 c ir reflow, peak temperature . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. terminology c d , c s (on) on sw itch capacitance. measured with refer- ence to ground. c in digital input capacitance. t on delay time between the 50% and 90% points of the stop condition and the switch ?n condition. t off delay time between the 50% and 90% points of the stop condition and the switch ?ff condition. t d ?ff?time measured between the 80% points of both switches when switching from one switch to another. charge a measure of the glitch impulse transferred from injection the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an ?ff?switch. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 dbs. on response the frequency response of the ?n?switch. insertion the loss due to the on resistance of the switch. loss warning! esd sensitive device v dd most positive power supply potential. i dd positive supply current. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. v d (v s ) analog voltage on terminals d, s. r on ohmic resistance between d and s. ? r on on resistance match between any two chan- nels, i.e., r on max ?r on min. r flat(on) flatness is de?ed as the difference between the maximum and minimum value of on resistance as measured over the speci?d analog signal range. i s (off) source leakage current with the switch ?ff. i d (off) drain leakage current with the switch ?ff. i d , i s (on) channel leakage current with the switch ?n. v inl maximum input voltage for logic ?. v inh minimum input voltage for logic ?. i inl (i inh ) input current of the digital input. c s (off) ?ff?switch source capacitance. measured with reference to ground. c d (off) ?ff?switch drain capacitance. m easured with reference to ground.
t a = 25 c v ss = 0v v dd = 4.5v v dd = 5.5v v dd = 3.3v v dd = 2.7v v d or v s ?drain or source voltage ?v on resistance ? 0 0 1 2 3 4 5 6 7 8 12345 figure 2. on resistance as a function of v d (v s ) for single supply current na 0.12 0 0.08 0.04 0.00 0.04 0.08 0.12 1 2345 v dd = 5v v ss = 0v t a = 25 c i d (on) i s (off) i d (off) v d (v s ) volts figure 5. leakage currents as a func- tion of v d (v s ) current na 0.05 15 0.05 0.15 0.20 0.30 0.35 25 temperature c 0.25 0.10 0.00 35 45 55 65 75 85 v dd = 3v v ss = 0v i d (off) i d (on) i s (off) figure 8. leakage currents as a func- tion of temperature typical performance characteristics ADG728/adg729 C7C rev. a v d or v s drain or source voltage v on resistance 0 0 1 2 3 4 5 6 7 8 1 2345 40 c +25 c v dd = 5v v ss = 0v +85 c figure 3. on resistance as a function of v d (v s ) for different temperatures, single supply current na 0.12 0 0.08 0.04 0.00 0.04 0.08 0.12 3.0 v d (v s ) volts 2.5 2.0 1.5 1.0 0.5 v dd = 3v v ss = 0v t a = 25 c i d (on) i d (off) i s (off) figure 6. leakage currents as a func- tion of v d (v s ) current a 1 10k 10 1m frequency hz 100 100k 1m v dd = 3v v dd = 5v t a = 25 c figure 9. input current vs. switch- ing frequency v d or v s drain or source voltage v on resistance 0 0 1 2 3 4 5 6 7 8 3.0 2.5 2.0 1.5 1.0 0.5 +25 c 40 c +85 c v dd = 3v v ss = 0v figure 4. on resistance as a function of v d (v s ) for different temperatures, single supply current na 0.05 15 0.05 0.15 0.20 0.30 0.35 25 temperature c 0.25 0.10 0.00 35 45 55 65 75 85 v dd = 5v v ss = 0v i d (on) i d (off) i s (off) figure 7. leakage currents as a function of temperature voltage volts q inj pc 40 0 30 20 10 0 10 20 1 2345 t a = 25 c v dd = 3v v ss = 0v v dd = 5v v ss = 0v figure 10. charge injection vs. source voltage
C8C rev. a ADG728/adg729 temperature c time ns 0 40 40 60 100 120 140 160 20 0 20 40 80 60 80 20 t on , v dd = 3v t off , v dd = 3v t on , v dd = 5v t off , v dd = 5v figure 11. t on /t off times vs. temperature frequency hz 0 30k attenuation db 5 100k 1m 10m 100m 10 15 20 v dd = 5v t a = 25 c ADG728 adg729 figure 14. on response vs. frequency frequency hz 0 30k attenuation db 20 40 60 80 100 120 100k 1m 10m 100m v dd = 5v t a = 25 c figure 12. off isolation vs. frequency frequency hz 0 30k attenuation db 20 40 60 80 100 120 100k 1m 10m 100m v dd = 5v t a = 25 c %&# 2
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ADG728/adg729 C9C rev. a general description the ADG728 and adg729 are serially controlled, 8-channel and dual 4-channel matrix switches respectively. while provid- ing the normal multiplexing and demultiplexing functions, these devices also provide the user with more flexibility as to where their signal may be routed. each bit of the serial word corre- sponds to one switch of the device. a logic 1 in the particular bit position turns on the switch, while a logic 0 turns the switch off. because each switch is independently controlled by an indi- vidual bit, this provides the option of having any, all, or none of the switches on. this feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). care must be taken, however, in the multiplexing situation where a number of inputs may be shorted together (separated only by the small on resistance of the switch). when changing the switch conditions, a new 8-bit word is writ- ten to the input shift register. some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. in order to minimize glitches on the output of these switches, the part cleverly compares the state of switches from the previous write cycle. if the switch is already in the on condition, and is required to stay on, there will be minimal glitches on the output of the switch. power-on reset on power-up of the device, all switches will be in the off con- dition and the internal shift register is ?led with zeros and will remain so until a valid write takes place. serial interface 2-wire serial bus the ADG728/adg729 are controlled via an i 2 c compatible serial bus. these parts are con nected to this bus as a slave de vice (no clock is generated by the multiplexer). the ADG728/adg729 have different 7-bit slave addresses. the ?e msbs of the ADG728 are 10011, while the msbs of the adg729 are 10001 and the two lsbs are determined by the state of the a0 and a1 pins. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address fol- lowed by a r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/w bit is high, the master will read from the slave device. however, if the r/ w bit is low, the master will write to the slave device. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established by the master. a stop condition is de?ed as a low-to-high transition on the sda line while scl is high. in write mode, the master will pull the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master will then bring the sda line low before the tenth clock pulse and then high during the tenth clock pulse to establish a stop condition. see figures 18 to 21 below for a graphical explanation of the serial interface. a repeated write function gives the user flexibility to update the matrix switch a number of times after addressing the part only once. during the write cycle, each data byte will update the con- ?uration of the switches. for example, after the matrix switch has acknowledged its address byte, and receives one data byte, the switches will update after the data byte, if another data byte is written to the matrix switch while it is still the addressed slave device, this data byte will also cause an switch con?uration update. repeat read of the matrix switch is also allowed. input shift register the input shift register is eight bits wide. figure 15 illustrates the contents of the input shift register. data is loaded into the device as an 8-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 1. the 8-bit word consists of eight data bits each controlling one switch. msb (bit 7) is loaded ?st. s8 s7 s6 s5 s4 s3 s2 s1 db0 (lsb) db7 (msb) data bits figure 15. ADG728/adg729 input shift register contents
C10C rev. a ADG728/adg729 write operation when writing to the ADG728/adg729, the user must begin with an address byte and r/ w bit, after which the switch will acknowledge that it is prepared to receive data by pulling sda low. this address byte is followed by the 8-bit word. the write operations for each matrix switch are shown in the ?ures below. scl sda s8 s7 s6 s5 s4 s3 s2 s1 00 1 1 a0r/ w stop cond by master ack by ADG728 start cond by master address byte data byte ack by ADG728 a1 1 figure 16. ADG728 write sequence scl sda s8 s7 s6 s5 s4 s3 s2 s1 00 1 a0r/ w stop cond by master ack by adg729 start cond by master address byte data byte ack by adg729 a1 1 0 figure 17. adg729 write sequence read operation when reading data back from the ADG728/adg729, the user must begin with an address byte and r/ w bit, after which the ma- trix switch will acknowledge that it is prepared to transmit data by pulling sda low. the readback operation is a single byte that consists of the eight data bits in the input register. the read operations for each part are shown in figures 18 and 19. scl sda s8 s7 s6 s5 s4 s3 s2 s1 00 1 a0r/ w stop cond by master ack by ADG728 start cond by master address byte data byte no ack by master a1 1 1 figure 18. ADG728 readback sequence scl sda s8 s7 s6 s5 s4 s3 s2 s1 00 1 a0r/ w stop cond by master ack by adg729 start cond by master address byte data byte no ack by master a1 1 0 figure 19. adg729 readback sequence
ADG728/adg729 C11C rev. a test circuits i ds s v s d v 1 r on = v 1 /i ds test circuit 1. on resistance i s (off) s1 s2 s8 d a gnd v dd v dd v d v s test circuit 2. i d (off) s1 s2 s8 d gnd v dd v dd v s a i d (off) v d test circuit 3. i s (off) s1 s8 d gnd v dd v dd v s a i d (on) v d test circuit 4. i d (on) gnd v dd v dd 50% t off 90% 90% 50% v s1 80% 80% v s1 = v s8 v out v out t on t open scl v out d v s1 ADG728* s1 s8 s2 thru s7 r l 300 c l 35pf v s8 * similar connection for adg729 test circuit 5. switching times and break-before-make times multiple devices on one bus figure 20 shows four ADG728s devices on the same serial bus. each has a different slave address since the state of their a0 and a1 pins is different. this allows each matrix switch to be writ- ten to or read from independently. because the adg729 has a different address to the ADG728, it would be possible for four of each of these devices to be connected to the same bus. ADG728 a1 a0 sda scl ADG728 a1 a0 sda scl ADG728 a1 a0 sda scl ADG728 a1 a0 sda scl scl sda +5v v dd master r p r p v dd v dd figure 20. multiple ADG728s on the same bus
ADG728/adg729 C12C rev. a printed in u.s.a. c01002C0C12/00 (rev. a) outline dimensions dimensions shown in inches and (mm). 16-lead tssop (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 sda v dd ADG728* 1nf input logic switch off switch on v out c l v s r s v out q inj = c l x v out d * similar connection for adg729 s v dd scl gnd test circuit 6. charge injection gnd ADG728* 50 s1 s2 s8 * similar connection for adg729 channel-to-channel crosstalk = 20log 10 (v out /v s ) v out v dd r l v dd 50 v s d test circuit 7. channel-to-channel crosstalk gnd ADG728* 50 s1 s8 v out v dd r l v dd v s d *similar connection for adg729 off isolation = 20log 10 (v out /v s ) v out without switch insertion loss = 20log 10 v out with switch s1 is switched off for off isolation measure- ments and on for bandwidth measurements test circuit 8. off isolation and bandwidth

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